Fused multiply add pipeline
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United States of America Patent
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Aug 30, 2016
Grant Date -
Aug 28, 2014
app pub date -
Jan 31, 2014
filing date -
Feb 27, 2013
priority date (Note) -
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Abstract
A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.
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