Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
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United States of America Patent
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Aug 30, 2016
Grant Date -
May 1, 2014
app pub date -
Oct 31, 2013
filing date -
Oct 31, 2012
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Abstract
A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.
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