Hierarchical negative bitline boost write assist for SRAM memory devices
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United States of America Patent
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Aug 30, 2016
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N/A
app pub date -
Nov 17, 2015
filing date -
Nov 17, 2015
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Abstract
A memory device having a plurality of banks of memory cells may be provided. Each memory cells may be interconnected via a local write bit-line and a complementary local write bit-line to a local write bit-line buffer circuit. The local write bit-line buffer circuit may be connected via a global write bit-line and a complementary one to a negative bias write assist circuit. The memory device may also comprise an address decoder separately connected to the local write bit-line buffer circuits. The address decoder may comprise a generating unit for enabling exactly one local write enable signal for a respective one of said local write bit-line buffer circuits. The local write bit-line buffer circuit may be adapted for generating local write data on said local write bit-line in response to receiving global write data on said global write bit-line when its local write enable signal is enabled.
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