Method and apparatus for per core performance states

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United States of America Patent

PATENT NO 9436254
APP PUB NO 20140229750A1
SERIAL NO

13976682

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Abstract

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A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhandaru, Malini K Sudbury, US 30 711
Bobholz, Scott P Bolton, US 17 447
Dehaemer, Eric J Shrewsbury, US 38 945
Ho, Samuel W Framingham, US 7 127
Poirier, Chris Fort Collins, US 12 95

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