Semiconductor device having shallow trench isolation and gate groove
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United States of America Patent
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Sep 6, 2016
Grant Date -
Feb 26, 2015
app pub date -
Aug 18, 2014
filing date -
Aug 26, 2013
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Abstract
Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode.
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