Write address synchronization in 2 read/1write SRAM arrays
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United States of America Patent
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Sep 6, 2016
Grant Date -
N/A
app pub date -
Mar 15, 2016
filing date -
Dec 4, 2015
priority date (Note) -
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Abstract
An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.
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