Implementing clock receiver with low jitter and enhanced duty cycle
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United States of America Patent
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Sep 6, 2016
Grant Date -
Jun 30, 2016
app pub date -
Dec 29, 2014
filing date -
Dec 29, 2014
priority date (Note) -
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Abstract
A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.
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