Transaction layer packet formatting

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9442855
APP PUB NO 20150161050A1
SERIAL NO

14583601

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Abstract

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A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONCALIFORNIA USA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ajanovic, Jasmin Portland, US 94 2793
Akiyama, James Beaverton, US 38 776
Barry, Peter Ardncrusha, IE 30 440
Bhatt, Ajay V Portland, US 30 1444
Blankenship, Robert G Tacoma, US 120 1209
Das, Sharma Debendra Saratoga, US 191 1587
Falik, Ohad Kfar Saba, IL 92 1935
Harriman, David J Portland, US 139 2343
Mendelson, Avi Haifa, IL 28 507
Muthrasanallur, Sridhar Bangalore, IN 51 1131
Pardo, Ilan Ramat-Hasharon, IL 69 926
Rodgers, Scott Dion Hillsboro, US 49 828
Rosenbluth, Mark B Uxbridge, US 84 1814
Sethi, Prashant Folsom, US 88 1543
Shamia, Doron Modiin, IL 26 514
Tamari, Eran Ramat Gan, IL 40 584
Vasudevan, Anil Portland, US 175 2371
Wagh, Mahesh Portland, US 117 1485
Weissmann, Eliezer Haifa, IL 186 2263

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