Memory system and assembling method of memory system

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United States of America Patent

PATENT NO 9443595
SERIAL NO

15001901

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Abstract

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According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nagai, Yuji Sagamihara, JP 144 609
Takeyama, Yoshikazu Fujisawa, JP 25 184

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