Patterning process for fin implantation
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United States of America Patent
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Sep 13, 2016
Grant Date -
Nov 26, 2015
app pub date -
May 20, 2014
filing date -
May 20, 2014
priority date (Note) -
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Abstract
After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.
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