Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function roll-off and improved negative bias temperature instability
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United States of America Patent
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Sep 13, 2016
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app pub date -
Aug 24, 2015
filing date -
Aug 24, 2015
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Abstract
A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate, where the source and the drain are positioned under the spacers. An interlayer dielectric is formed on top of the substrate, the spacers, and the dummy gate. The interlayer dielectric is planarized along with part of the spacers and the dummy gate. The dummy gate is removed, thereby leaving an opening. A sacrificial layer is deposited on top of the substrate in a bottom of the opening. The sacrificial layer includes at least one of silicon germanium and/or germanium. The sacrificial layer is removed from the substrate in the bottom of the opening, thereby growing an interfacial oxide layer on the substrate in the opening. A high-κ dielectric layer is deposited on top of the interfacial oxide layer.
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