Memory subsystem and computer system

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9448953
APP PUB NO 20140025855A1
SERIAL NO

13945330

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Abstract

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The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujita, Norio Shiga-Ken, JP 23 458
Hori, Masahiro Shiga-ken, JP 66 1152
Murakami, Masahiro Kyoto, JP 132 769
Okazawa, Junka Kyoto, JP 19 56

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