Controlling operation of a timing device using an OTP NVM to store timing device configurations in a RAM
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United States of America Patent
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Sep 27, 2016
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N/A
app pub date -
Apr 20, 2015
filing date -
Apr 20, 2015
priority date (Note) -
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Abstract
The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is configured to store the configuration data from the OTP NVM beginning at an address in the RAM corresponding to a read start address to define a timing device configuration in the RAM.
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