Receiver with clock recovery circuit and adaptive sample and equalizer timing

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United States of America Patent

PATENT NO 9455825
SERIAL NO

14868721

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Abstract

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A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

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Patent Owner(s)

  • RAMBUS INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Hae-Chang Los Altos, US 80 729
Leibowitz, Brian San Francisco, US 38 688
Lin, Qi Los Altos, US 86 976
Oh, Kyung Suk Cupertino, US 116 1011
Ren, Jihong Sunnyvale, US 46 782
Zerbe, Jared L Woodside, US 215 5652

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