Data decoder with trapping set flip bit mapper

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United States of America Patent

PATENT NO 9459956
APP PUB NO 20150026536A1
SERIAL NO

13958162

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Abstract

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A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.

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Patent Owner(s)

  • SEAGATE TECHNOLOGY LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alhussien, AbdelHakim S Milpitas, US 69 849
Chen, Zhengang Milpitas, US 118 1514
Hubris, Alexander Milpitas, US 16 228
Wu, YingQuan Milpitas, US 72 888

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