Formal verification driven power modeling and design verification
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United States of America Patent
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Oct 4, 2016
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N/A
app pub date -
Apr 27, 2016
filing date -
Feb 11, 2016
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Abstract
A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
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