Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

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United States of America Patent

PATENT NO 9465647
SERIAL NO

14048451

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Abstract

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In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONSANTA CLARA CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Binns, Frank Portland, US 26 576
Datta, Shamanna M Hillsboro, US 22 236
Doshi, Gautam Bangalore, IN 11 150
Ganesan, Baskaran Bangalore, IN 25 209
Kumar, Mohan J Aloha, US 227 3037
Murthy, Rajesh Nagaraja Bangalore, IN 4 31
Natu, Mahesh Sunnyvale, US 29 342
Parthasarathy, Rajesh S Hillsboro, US 32 631
Rangarajan, Thanunathan Bangalore, IN 22 262
Swanson, Robert C Olympia, US 78 1391

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