Packaged semiconductor device for high performance memory and logic
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United States of America Patent
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Oct 11, 2016
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N/A
app pub date -
Jul 29, 2010
filing date -
Aug 6, 2009
priority date (Note) -
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Abstract
A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.
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