Multi-chips in system level and wafer level package structure
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United States of America Patent
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Oct 11, 2016
Grant Date -
Jun 16, 2016
app pub date -
Feb 22, 2016
filing date -
Jan 16, 2013
priority date (Note) -
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Abstract
A multi-chips in system level and wafer level package structure includes a package substrate having a plurality of through holes a multi-chips with different functions and sizes, the metal wires, a package body, and the conductive components. The multi-chips are used to combine with the package substrate so as to the pads of the multi-chips are exposed out of the through holes. The pads of the multi-chips are electrically connected to the connecting terminal adjacent to the through holes by the plurality of conductive wires. The package material is filled into the through holes to form the package body to encapsulate the conductive wire, each active surface and the pads of the multi-chips with the different functions and the sizes by dispensing method so as to the multiple chip system level and wafer level package structure is accomplished by partially packaging method.
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