Stress-reduced circuit board and method for forming the same
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United States of America Patent
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Oct 11, 2016
Grant Date -
Apr 24, 2014
app pub date -
Aug 7, 2013
filing date -
Oct 18, 2012
priority date (Note) -
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Abstract
A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.
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