Methods of fabricating memory devices using wet etching and dry etching
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United States of America Patent
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Nov 1, 2016
Grant Date -
Mar 3, 2016
app pub date -
Aug 14, 2015
filing date -
Aug 27, 2014
priority date (Note) -
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Abstract
A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.
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