Interconnect structures for wafer level package and methods of forming same

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9484285
APP PUB NO 20160056056A1
SERIAL NO

14464487

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Abstract

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A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Meng-Tse Changzhi Township, TW 100 1568
Cheng, Ming-Da Jhubei, TW 447 4774
Huang, Hui-Min Taoyuan, TW 110 1043
Lin, Chih-Wei Zhubei, TW 359 5145
Liu, Chung-Shi Hsin-Chu, TW 824 11367
Yu, Chen-Hua Hsin-Chu, TW 2207 47923

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