Semiconductor devices with close-packed via structures having in-plane routing and method of making same
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United States of America Patent
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Nov 1, 2016
Grant Date -
Feb 4, 2016
app pub date -
Oct 13, 2015
filing date -
Mar 12, 2012
priority date (Note) -
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Abstract
The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.
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