Reduced memory vectored DSL
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 8, 2016
Grant Date -
Jul 31, 2014
app pub date -
Apr 1, 2014
filing date -
Jul 1, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A reduced-memory vectored DSL system reduces the bandwidth and memory storage demands on a vectored DSL system in which FEXT data is transmitted and stored. When test signal data, such as training and/or tracking data, is sent to determine FEXT characteristics of the DSL system, error signals are available for all or substantially all of the upstream and/or downstream frequency band DSL tones used in the system. Dividing a frequency band into sub-bands, only a subset of tones in each sub-band is used for deriving FEXT data. For tones in the sub-band subsets, full-precision FEXT data values can be derived. For other tones, approximations of the FEXT data can be derived. Memory is reduced in both the transmission of such FEXT data (between upstream and downstream ends) and within an upstream-end device such as a DSLAM that performs vectoring using a separate or internal vectoring processing apparatus.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully