Reestablishing synchronization in a memory system
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United States of America Patent
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Nov 15, 2016
Grant Date -
Jun 30, 2016
app pub date -
Mar 17, 2016
filing date -
Mar 15, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.
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