Secondary use of aspect ratio trapping holes as eDRAM structure
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United States of America Patent
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Nov 15, 2016
Grant Date -
Jun 2, 2016
app pub date -
Jan 22, 2016
filing date -
Sep 30, 2014
priority date (Note) -
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Abstract
A semiconductor structure is provided according to a method in which an aspect ratio trapping process is employed. The structure includes a semiconductor substrate comprising a first semiconductor material having a first lattice constant. A first layer of second semiconductor material formed on the substrate, the first layer having a second lattice constant that is greater than the first lattice constant. A second layer of a semi-insulating, third semiconductor material is formed atop a top surface of the first layer. A transistor device is formed on top of the second layer. An eDRAM structure is connected electronically with a channel region of the transistor device, the eDRAM structure extending from the channel region of the transistor device to a sub-surface below a top surface of the semiconductor substrate.
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