Low-noise sampled voltage regulator
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United States of America Patent
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Nov 22, 2016
Grant Date -
Jul 14, 2016
app pub date -
Jan 12, 2015
filing date -
Jan 12, 2015
priority date (Note) -
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Abstract
A method and voltage regulator comprises a generator that generates an error difference between a reference and regulated voltage. A clocked ADC samples the voltage as a digital stream. A DAC converts the stream to analog signal(s). A current source driven by the signal(s) generate(s) the regulated voltage. The generator may be an op-amp or comparator comprising a buffer and/or a latch. The N-bit ADC may be a Σ-Δ modulator or N 1-bit ADC latches. The N-bit DAC may comprise 1-bit DACs comprising a switched-capacitor summer and a one stage RC LPF. Sampling the error up-converts flicker noise to the clock frequency which the DAC filters out. The current source may comprise N transistors with gates driven by a signal and sources tied to an independent power supply. Each signal may be weighted by a DAC weight. The apparatus may comprise a decoupling capacitor between the regulated voltage and ground.
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