Instruction and logic for store broadcast and power management

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9501132
APP PUB NO 20160041945A1
SERIAL NO

14453341

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Abstract

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A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kurolap, Yulia Haifa, IL 3 18
Mishaeli, Michael Zichron Yaakov, IL 53 497
Ofir, Gal Atzmon, IL 9 108
Shwartsman, Stanislav Haifa, IL 53 384

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