Instructions and logic to vectorize conditional loops

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United States of America Patent

PATENT NO 9501276
APP PUB NO 20140189321A1
SERIAL NO

13731809

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In response to the processor instruction, data is copied from consecutive vector elements in the source vector, and expanded into unmasked vector elements of the specified destination vector, without copying data into masked vector elements of the destination vector, wherein n varies responsive to the processor instruction executed. The source vector may be a register and the destination vector may be in memory. Some embodiments store counts of the condition decisions. Alternative embodiments may store other data, for example such as target addresses, or table offsets, or indicators of processing directives, etc.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ould-Ahmed-Vall, Elmoustapha Chandler, US 571 3482
Toll, Bret L Hillsboro, US 162 1329
Uliel, Tal Tel Aviv, IL 31 191

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