Memory device
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United States of America Patent
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Nov 22, 2016
Grant Date -
Sep 10, 2015
app pub date -
Aug 13, 2014
filing date -
Mar 5, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment, an encoder generates a write data parity from write data to memory elements. A decoder corrects an error of read data from the memory elements using a read data parity for the read data and a check matrix. An inverter maintains or inverts all bits of a received input. Calculation by the decoder using the read data, the read data parity, and the check matrix produces a first result when an error is not included in the read data, a second result when an error is included in the read data, a third result when an error is not included in the read data and all bits of the read data are inverted, and a fourth result when an error is included in the read data and all bits of the read data are not inverted.
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