Protocol for memory power-mode control
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United States of America Patent
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Nov 22, 2016
Issued Date -
N/A
app pub date -
Dec 17, 2014
filing date -
Feb 23, 2011
priority date (Note) -
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Abstract
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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