Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor

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United States of America Patent

PATENT NO 9507656
APP PUB NO 20100268920A1
SERIAL NO

12424929

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Abstract

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A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.

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Patent Owner(s)

Patent OwnerAddress
ORACLE AMERICA INC500 ORACLE PARKWAY MAIL STOP 5OP7 REDWOOD SHORES CA 94065

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brooks, Jeffrey S Austin, US 78 989
Jordan, Paul J Austin, US 36 781
Olson, Christopher H Austin, US 66 960

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