Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor
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United States of America Patent
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Nov 29, 2016
Grant Date -
Oct 21, 2010
app pub date -
Apr 16, 2009
filing date -
Apr 16, 2009
priority date (Note) -
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Abstract
A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.
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