Integrated circuit package substrate
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United States of America Patent
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Nov 29, 2016
Issued Date -
N/A
app pub date -
Oct 16, 2013
filing date -
Oct 16, 2013
priority date (Note) -
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Abstract
Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
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