3D stacked semiconductor memory architecture with conductive layer arrangement
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United States of America Patent
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Nov 29, 2016
Grant Date -
May 19, 2016
app pub date -
Jan 27, 2016
filing date -
Jun 17, 2011
priority date (Note) -
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Abstract
According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.
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