Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment

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United States of America Patent

PATENT NO 9512863
APP PUB NO 20140147192A1
SERIAL NO

13871830

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Abstract

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A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

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Patent Owner(s)

Patent OwnerAddress
CALIFORNIA INSTITUTE OF TECHNOLOGY1200 E CALIFORNIA BLVD M/C 6-32 PASADENA CA 91125

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chattopadhyay, Goutam Pasadena, US 30 773
Cooper, Ken B Glendale, US 7 256
Gill, John J La Crescenta, US 7 264
Jung-Kubiak, Cecile Pasadena, US 6 20
Lee, Choonsup La Palma, US 19 778
Lin, Robert H Chino, US 7 18
Mehdi, Imran South Pasadena, US 12 507
Peralta, Alejandro Huntington Beach, US 6 10
Reck, Theodore Pasadena, US 4 7
Siles, Jose V Pasadena, US 3 14
Thomas, Bertrand Bonn, DE 8 6
Toda, Risaku Glendale, US 17 153

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