Enhanced computer processor and memory management architecture
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United States of America Patent
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Dec 6, 2016
Grant Date -
N/A
app pub date -
May 23, 2013
filing date -
May 24, 2012
priority date (Note) -
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Abstract
Disclosed in some examples is an improved computing architecture, which includes multiple processor cores and I/O devices communicating with multiple memory banks using a High Speed Interconnect Unit (HSU). The HSU quickly routes (e.g., in one clock cycle) a memory access request from an I/O device or a processor core to a particular memory bank over one of a number of independent memory routes, each memory route servicing a particular memory bank. The routing is based upon the values of preselected bit positions (“preselected bits”) in the requested memory address, the preselected bits being chosen so as to maximize the distribution of memory accesses of the entire system across all available memory banks (and by extension distributing the memory accesses across the available memory routes).
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