Electroless metal through silicon via
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United States of America Patent
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Dec 6, 2016
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N/A
app pub date -
Sep 27, 2013
filing date -
Sep 27, 2012
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Abstract
A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 μm are provided on both sides of the wafer.
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