Timing synchronization circuit with loop counter
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United States of America Patent
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Dec 27, 2016
Grant Date -
Sep 11, 2014
app pub date -
May 19, 2014
filing date -
Dec 19, 2006
priority date (Note) -
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Abstract
An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.
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