Topology specific replicated bus unit addressing in a data processing system
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United States of America Patent
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Dec 27, 2016
Grant Date -
N/A
app pub date -
Mar 28, 2016
filing date -
Dec 7, 2015
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Abstract
A technique for handling cache-inhibited operations in a data processing system includes receiving, at a replicated bus unit, a cache-inhibited (CI) operation. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is associated with the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being associated with the replicated bus unit, the replicated bus unit processes the CI operation. In response to the address associated with the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being associated with the replicated bus unit, the replicated bus unit ignores the CI operation.
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