Protective trench layer and gate spacer in finFET devices
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United States of America Patent
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Dec 27, 2016
Grant Date -
Dec 24, 2015
app pub date -
Jun 24, 2014
filing date -
Jun 24, 2014
priority date (Note) -
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Abstract
Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.
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