Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch
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United States of America Patent
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Dec 27, 2016
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N/A
app pub date -
Jan 28, 2016
filing date -
Jan 28, 2016
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Abstract
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.
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