Apparatus and method to transfer data packets between domains of a processor
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United States of America Patent
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Jan 3, 2017
Grant Date -
Mar 31, 2016
app pub date -
Sep 26, 2014
filing date -
Sep 26, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.
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