Memory module capable of handshaking with a memory controller of a host system
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United States of America Patent
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Jan 3, 2017
Issued Date -
N/A
app pub date -
Jun 1, 2016
filing date -
Jun 12, 2009
priority date (Note) -
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Abstract
A memory module is operable with a memory controller of a host computer system. The memory module includes a module controller having an open drain output. The module controller generates a parity error signal and drives the parity error signal to the memory controller of the host system via the open drain output while the memory module operates in a first mode, the parity error signal indicating a parity error having occurred in the memory module while the memory module operates in the first mode. The module controller is configured to cause the memory module to enter a second mode in response to a command from the memory controller of the host system. The module controller generates a notification signal indicating at least one status of one or more training sequences while the memory module is in the second mode and outputs the notification signal to the memory controller of the host system via the open drain output while the memory module is in the second mode.
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