Method and apparatus for asynchronous processor removal of meta-stability

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United States of America Patent

PATENT NO 9535698
APP PUB NO 20150074445A1
SERIAL NO

14480522

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Abstract

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A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

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Patent Owner(s)

  • HUAWEI TECHNOLOGIES CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ge, Yiqun Ottawa, CA 90 613
Huang, Tao Ottawa, CA 265 1233
Shi, Wuxian Ottawa, CA 53 432
Tong, Wen Ottawa, CA 640 17203
Zhang, Qifan Lachine, CA 35 260

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