Processing system with interspersed processors and communication elements having improved communication routing
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United States of America Patent
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Jan 3, 2017
Grant Date -
Nov 27, 2014
app pub date -
Aug 5, 2014
filing date -
Jun 26, 2002
priority date (Note) -
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Abstract
A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.
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