Optimization of integrated circuit physical design
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United States of America Patent
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Jan 3, 2017
Grant Date -
Dec 17, 2015
app pub date -
Jun 12, 2014
filing date -
Jun 12, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment of the present invention, a method for optimizing an integrated circuit design is provided. The method may include identifying one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic. The method may include inserting interior buffers on the nets inside of the child block and exterior buffers on the nets outside of the child block and inside of the parent block, wherein the interior buffers and the exterior buffers define a buffer pair for each of the nets. The method may further include determining a first placement for the parent logic and a second placement for the child logic, such that the buffers of the buffer pair for each net are placed substantially near to one another. The method may further include determining pin locations for the child block based on the second placement.
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