Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9536863
APP PUB NO 20130313709A1
SERIAL NO

13994919

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Halbert, John B Beaverton, US 90 5342
Hinck, Todd A Arlington, US 10 83
Martin, Aaron El Dorado Hills, US 67 336
Martwick, Andrew W Portland, US 35 858
Wu, Zuoguo San Jose, US 68 314

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