Gate pad and gate feed breakdown voltage enhancement
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United States of America Patent
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Jan 3, 2017
Grant Date -
Jun 9, 2016
app pub date -
Feb 12, 2016
filing date -
Mar 13, 2013
priority date (Note) -
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Abstract
A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers.
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