Methods for calibrating a read data path for a memory interface
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United States of America Patent
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Jan 24, 2017
Grant Date -
Oct 22, 2015
app pub date -
Jun 27, 2015
filing date -
Jun 6, 2008
priority date (Note) -
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Abstract
A method for calibrating a read data path for a DDR memory interface circuit from time to time in conjunction with functional operation of a memory circuit is described. The method uses the steps of issuing a sequence of read commands so that a delayed dqs signal toggles continuously. Next, delaying a core clock signal originating within the DDR memory interface circuit to produce a capture clock signal. The capture clock signal is delayed from the core clock by a capture clock delay value. Next, determining an optimum capture clock delay value. The output of the read data path is clocked by the core clock. The timing for the read data path with respect to data propagation is responsive to at least the capture clock.
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